1. Field of the Invention
The present invention relates to an improvement of a manufacturing process for a semiconductor device. More particularly, it relates to a control system for a plurality of manufacturing processes and a method for controlling a sequence of manufacturing processes. The control system is capable of suppressing crystal defects in the manufacturing processes for a semiconductor integrated circuit.
2. Description of the Related Art
In a sequence of manufacturing processes of a semiconductor device such as a large scale integrated circuit (LSI), generation of a dislocation of a process-induced crystal defect causes problem with the electrical characteristics of the LSI such as leakage current in a pn junction. Accordingly, the product yield rate is significantly decreased. Particularly, a semiconductor substrate has grown in size to have a diameter of 300 mm. Thus, manufacturing costs of the semiconductor device have increased. Once an electrical characteristic failure occurs in a semiconductor device of a product lot, an attempt is made to identify the failure, and measures to prevent the cause of the failure are investigated. Currently, in order to search for the cause of the failure, a plurality of prototype lots are manufactured by changing process conditions in trial facilities, and an electrical characteristic, stress simulation and the like, are evaluated for a semiconductor device of each prototype lot. By referring to the evaluation results of the semiconductor devices, the reason for generation of a dislocation is identified. Then, measures to prevent the reason for generation of the dislocation can be taken. However, the current stress simulation provides only a distribution of stress and distortion. Thus, it is very ambiguous whether a dislocation actually occurs, since growth of the dislocation is separately determined. Therefore, in the current situation, enormous stress simulation results are hardly ever used in searching for a cause of dislocation generation.
As to evaluation of a dislocation in a semiconductor device, a dislocation dynamics simulation has been proposed which deals with dislocation motion and an interaction between dislocations in a three-dimensional stress field based on dislocation dynamics (see K. W. Schwarz, J. Appl. Phys., January 1999, Vol. 85, No. 1, p. 108). Although the dislocation dynamics simulation has a large potential, cases dealing with the dislocation dynamics simulation are limited to a behavior of a dislocation in a relatively simple dislocation pattern. Therefore, the dislocation dynamics simulation has not yet been established as an effective means for investigating a cause of dislocation generated in the semiconductor device.
Moreover, in order to search for a cause of a failure, evaluation of a semiconductor device manufactured for a prototype, under a number of process conditions, is time-consuming. Since the manufacture of product lots is continued during a search for a cause of a failure, a number of product lots will be wasted before a measure or a preventive measure to cure the cause of the failure is taken. Therefore, the yield rate for a semiconductor device drastically decreases, and the manufacturing costs increase.